nvc.com - releases

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		Actis Design, LLC: EETimes--ESL startups ink deals with European distributors EETimes--Firms collaborating on SystemC Design Calypto: EETimes--Calypto adds VHDL support to PowerPro CG EDA DesignLine--Reducing Power Consumption in a Fiber Channel Switch SOCcentral--Formal Verification Goes Mainstream IC Design and Verification Journal--ESL Gets a New Taker EDA DesignLine--The power of sequential design optimizations EETimes--Cadence introduces C-to-silicon complier SCDsource--Cadence claims 'next generation' high-level synthesis EDN--Cadence C-to-Silicon Synthesis may mark next round in ESL tools EETimes--Are IC thermal problems hot air? DACeZine--Facing Down The Perfect Storm Portable Design--Calypto and Cadence Deliver Optimized Power Flow SOCcentral--ESL Is Finally Ready For Prime Time DACeZine--Where is innovation happening in EDA these days? IC Design and Verification Journal--Attacking Abuses of Power - Part 2 Wireless Design & Development-- Register Transfer Level (RTL) power optimization tools eliminate need for error-prone manual methods IC Design and Verification Journal--Attacking Abuses of Power - Part 1 EETimes--Hardware design using ESL EDN--My IC reliability cover story and my upcoming DesignCon DFM panel EDA Design Line--Utilizing Clock-Gating Efficiency to Reduce Power SCDsource--Sequential equivalence checker supports C synthesis tools Carbon Design Systems: EETimes--Carbon Design releases latest SoC Designer EETimes--Virtual prototypes speed wireless development Electronic Design--Expect New Consumer Electronics Devices Thanks to TLM 2.0 Embedded Computing Design--Modeling techniques maximize value of virtual platforms Electronic Design--Hardware/Software Co-Design Comes Of Age Mass High Tech--Carbon Design plans out West Coast future of new ARM EDA Design Line--Two good British deals, and the advent of Mentorence Portable Design--Carbon Design Systems Acquires SoC Designer from ARM SCDsource--Carbon acquires ARM tool, sources cycle-accurate models EETimes--Carbon Design Systems acquires SoC designer from ARM Embedded.com--Leveraging Virtual Hardware Platforms for Embedded Software Validation: Part 2 Embedded.com--Leveraging virtual hardware platforms for embedded software validation Portable Design--Enhanced Carbon Model Studio Reduces Time to Create Models IC Design and Verification Journal--Trans-Acting Lessons: Modeling and Transactors for the Simulation and Emulation World Electronic Design--45th DAC Takes The SoC Methodology Plunge SOCcentral--ESL Is Finally Ready For Prime Time Chip Design--Make Verification Work with Multiple Levels of Abstraction/a> Chip Design--Wither ESL 2.0--Are you ready to bite the bullet? DACeZine--Education: A Lifelong Adventure EETimes--Applying incremental simulation techniques EDA Weekly--Fireside Chat: Rick Lucier & Jim McCanny EETimes--Carbon Design raises $6 million SCDsource--Virtual platforms--a reality check, part 2 EDA Tech Forum--Using a 'divide and conquer' approach to system verification CEDA: Electronic Design--EDA Consortium, IEEE Council On EDA Jointly Sponsor Kaufman Awared Chip Design--DOT.ORG: Introducing CEDA: An Organization for the CAD Community Design Automation Conference (DAC): Electronic Design--DAC: Let The Games Begin EDN--DAC technical program will go beyond the IC EVE: System-Level Design Community--Devil In The Details: Trends in ASIC Prototyping Electronic Design--For Checking Software Without Hardware, FPGAs Are The Answer Electronic Design--Debugging SoCs Is More Complex Than Finding A Needle In A Haystack Chip Design--Indian Semiconductor Market Embraces Hardware-Assisted Verification Solutions Pradeep Chakraborty's Blog--EVE betting strong on Indian semicon industry CIOL--Indian semicon industry attractive for EVE EDA DesignLine--Surveying the hardware-assisted verification landscape Electronic Design--Hardware/Software Co-Design Comes Of Age Electronic Design--A Mid-Year Check On The Optimism Meter SCDsource--DAC panelists discuss 'electronics and politics' EETimes--High-tech will relieve energy crisis--some day EETimes--Design News: EDA still software challenged IC Design and Verification Journal--Trans-Acting Lessons: Modeling and Transactors for the Simulation and Emulation World Chip Design--[Top View]Performance and Cost Now Drive Emulation Electronic Design--DAC Tackles Emulation, Speed And Standards The New York Times--In Today's Air Travel, Stress and Comfort Mix DACeZine--Same Problems, Different Answers DACeZine--Using a Bit of French-Inspired Creativity to Navigate the Silicon Valley Magic Chip Design--Wither ESL 2.0--Are you ready to bite the bullet? EDA Design Line--EVE in the Systems Prototyping Garden Portable Design--SoC Hardware Verification Platform Electronic Design--Optimism Abounds For Emulation Sector In 2008 EETimes--Viewpoint: How to manage a billion cycles Electronic Design--EVE and CoWare Forge Strategic Alliance Programmable Logic DesignLine--EVE and CoWare link ESL to HW/SW coverification EETimes--EVE links up with CoWare Chip Design--Head-to-Head: Three Views on Verification Challenges Imperas: EETimes--Video: Searching for ROI in virtual platforms ECN--Virtual Platform Speed Code Development for Multi-Core SoCs Embedded Computing Design--OVP makes system-level virtual protptyping a reality Electronic Design--Hardware/Software Co-Design Comes Of Age EDACafe--"Blue Ocean Strategy" + OVP (Open Virtual Platform) EETimes--Design News: EDA still software challenged DACeZine--Same Problems, Different Answers DACeZine--Nightmare Scenario--Will Moore's Law Put the EDA Industry Out of Business? Electronic Design--You Say You Want a Revolution, You'll Find One In OVP SCD Source--Panelists clash over virtual platform standards SCD Source--Why today's virtual platforms aren't the answer Embedded Technology Journal--Seeding Multicore Infrastructure Portable Design--Open Virtual Platforms for Virtual Prototyping, Embedded Software Development SCD Source--Virtutech seeks to drive virtual platform standards EETimes--Standards advance for virtual prototyping SCD Source--Imperas donates 'open' virtual platform infrastructure EETimes--Imperas donation forms open-source virtual platform initiative Magma: SOCcentral--Single, Unified Datamodel Key to Integrated IC Implementation Flow SOCcentral--Deep Submicron Designs Challenge Physical Implementation Tools Electronic Products--Design tool focuses on porting challenges IC Design and Verification Journal--Full Frontal Attack EETimes--Analysis: What's wrong with Magma? IC Design and Verification Journal--Play It Again, Sam Electronic Design--Yield Enhancement Software To Aid Solar Cell Fabs EDN--Synopsys, Magma eye opportunities in solar market EETimes--Magma converts EDA software for use in solar fab Silicon Valley/San Jose Business Journal--Silicon Valley's 40 Under 40 Portable Design--Unified Power Format to Simplify Low-Power Design Flows EDA Confidential--Start-ups, Silicon Valley and EDA SCDsource--DAC panelists discuss 'electronics and politics' EETimes--High-tech will relieve energy crisis--some day Portable Design--Magma Introduces Flexible, Automated Floorplan Synthesis Product IC Design and Verification Journal--Sticking to Plan Electronic Design--45th DAC Takes The SoC Methodology Plunge Chip Design--Max's Chips and Dips: Automated, Full-Chip Mixed-Signal Design Solution DACeZine--Nightmare Scenario--Will Moore's Law Put the EDA Industry Out of Business? Chip Design--Chip-Package-Board Co-Design: It's a Brave New World Chip Design--Max's Chips and Dips: Chip-Package-Board Co-Design...It's a Brave New World Electronic Design--Low-Power Reference Flow Targets UMC's Advanced 65-nm Process Electronic Design--Keys To Improving Yield EETimes--Analog tools must catch up SCDsource--How Synopsys' Synplicity buy impacts ASIC, FPGA designers SCDsource--Five trends drive shift to 'design-driven' verification EETimes--Comment: IP adventures in EDA IC Design and Verification Journal--A Merger of Unequals SCDsource--Synopsys pledges multicore support for EDA applications Portable Design--Custom Platform Combines Full-Chip, Mixed-Signal, Analysis and Verification for IC Design Electronic Design--Magma Rolls Full-Chip, Mixed-Signal Design/Verification Suite IC Design and Verification Journal--Attacking Abuses of Power - Part 1 Electronic Design--Bring More Automation Into Mixed-Signal Design Electronic Design--Power-Intent Standards Vie For Designers' Loyalties DACeZine--Will there be more startups in EDA? EDA Design Line--Physically Aware Test Development EDN--Magma makes DRC incremental with Talus QDRC, plans transistor level extractor EDA Design Line--Viewpoint: Power Format Battles Over EDA Tech Forum--EDA vendors are driving a new standard through Accellera, explains Yatin Trivedi Pulsic: SCDsource--Flash memory demands custom design automation Electronic Design--Anaolg/Full-Custom Flows Move Toward Interoperability Verific Design Automation: EETimes--Commentary: EDA industry needs revitalizing Chip Design--The Emergence of EDA Component Software Willamette HDL: SCDsource--Open Verification Methodology allows resuable testbenches		Color
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Color	"I have worked with the delightful Nanette Collins for more than six years, spanning three companies. Nanette is the ultimate in a proactive PR professional (sometimes I think that I work for her!). We never worry about anything slipping through the cracks, her follow-up is as complete as it gets." Steve Carlson, Group Director, R & D Cadence Design Systems			Color